1) An Assert is ______ command.
a. Sequential
b. Concurrent
c. Both a and b
d. None of the above
|
Answer
Explanation
|
ANSWER: Both a and b
Explanation:
No explanation is available for this question!
|
|
2) The 'next' statements skip the remaining statement in the ________ iteration of loop and execution starts from first statement of next iteration of loop.
a. Previous
b. Next
c. Current (present)
d. None of the above
|
Answer
Explanation
|
ANSWER: Current (present)
Explanation:
No explanation is available for this question!
|
|
3) Which among the following wait statement execution causes the enclosing process to suspend and then wait for an event to occur on the signals?
a. Wait until Clk = '1'
b. Wait on x,y,z
c. Wait on clock until answer > 80
d. Wait for 12 ns
|
Answer
Explanation
|
ANSWER: Wait on x,y,z
Explanation:
No explanation is available for this question!
|
|
4) In composite data type of VHDL, the record type comprises the elements of _______data types.
a. Same
b. Different
c. Both a and b
d. None of the above
|
Answer
Explanation
|
ANSWER: Different
Explanation:
No explanation is available for this question!
|
|
5) Which among the following is pre-defined in the standard package as one-dimensional array type comprising each element of BIT type?
a. Bit type
b. Bit_vector type
c. Boolean type
d. All of the above
|
Answer
Explanation
|
ANSWER: Bit_vector type
Explanation:
No explanation is available for this question!
|
|
6) In VHDL, which class of scalar data type represents the values necessary for a specific operation?
a. Integer types
b. Real types
c. Physical types
d. Enumerated types
|
Answer
Explanation
|
ANSWER: Enumerated types
Explanation:
No explanation is available for this question!
|
|
7) Which data type in VHDL is non synthesizable & allows the designer to model the objects of dynamic nature?
a. Scalar
b. Access
c. Composite
d. File
|
Answer
Explanation
|
ANSWER: Access
Explanation:
No explanation is available for this question!
|
|
8) In VHDL, which object/s is/are used to connect entities together for the model formation?
a. Constant
b. Variable
c. Signal
d. All of the above
|
Answer
Explanation
|
ANSWER: Signal
Explanation:
No explanation is available for this question!
|
|
9) In Net-list language, the net-list is generated _______synthesizing VHDL code.
a. Before
b. At the time of (during)
c. After
d. None of the above
|
Answer
Explanation
|
ANSWER: After
Explanation:
No explanation is available for this question!
|
|
10) Among the VHDL features, which language statements are executed at the same time in parallel flow?
a. Concurrent
b. Sequential
c. Net-list
d. Test-bench
|
Answer
Explanation
|
ANSWER: Concurrent
Explanation:
No explanation is available for this question!
|
|
